Port Registers (Pdr0 To Pdra) - Fujitsu MB90480 Series Hardware Manual

F2mc-16lx 16-bit microcontroller

Table of Contents

CHAPTER 8 I/O PORT

Port registers (PDR0 to PDRA)

This section shows the configuration and explains the functions of port registers

(PDR0 to PDRA)

Port registers (PDR0 to PDRA)

Figure 8.2-1 shows a list of port registers (PDR0 to PDRA).

Address:000000

Address:000001

Address:000002

Address:000003

Address:000004

Address:000005

Address:000006

Address:000007

Address:000008

Address:000009

Address:00000A

*1: R/W access to I/O ports slightly differs in operation from R/W access to memory. Be careful about such

R/W access because it operates as follows:

- 0: Input mode

-- During reading: The level of the relevant pins is read and output.

-- During writing: Writing is performed on the latch for output.

- 1: Output mode

- During reading: The value of the data register latch is read and output.

- During writing: Output is to the relevant pins.

*2: The initial value of MB90485 series is "11XXXXXX

Figure 8.2-1 List of port registers (PDR0 to PDRA)

Initial value