Address Detection Control Register (Pacsr) - Fujitsu F2MC-16LX Hardware Manual

24.3.1

Address Detection Control Register (PACSR)

The address detection control register (PACSR) enables or disables output of an
interrupt at an address match. When an address match is detected when output of an
interrupt at an address match is enabled, the INT9 interrupt is generated.
Address Detection Control Register (PACSR)
7 6
5
Reserved Reserved Reserved Reserved
R/W R/W R/W
R/W : Read/Write
: Reset value
Figure 24.3-2 Address Detection Control Register (PACSR)
4 3 2 1 0
AD1E AD0E
Reserved Reserved
R/W R/W R/W R/W R/W
bit 0
Reserved
bit 1
AD0E
bit 2
Reserved
bit 3
AD1E
bit 4
Reserved
bit 5
Reserved
bit 6
Reserved
bit 7
Reserved
CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION
Reset value
0 0 0 0 0 0 0 0
B
Reserved bit
0 Always set to "0"
Address match detection enable bit 0
0
Disables address match detection in PADR0
1
Enables address match detection in PADR0
Reserved bit
0 Always set to "0"
Address match detection enable bit 1
0 Disables address match detection in PADR1
1 Enables address match detection in PADR1
Reserved bit
Always set to "0"
0
Reserved bit
0 Always set to "0"
Reserved bit
0 Always set to "0"
Reserved bit
0 Always set to "0"
Address
009E
H
551