Fujitsu MB90480 Series Hardware Manual page 410

CHAPTER 18 EXPANDED I/O SERIAL INTERFACE
● Setting when using as SIN1/SCK1/SIN2/SCK2 pins
When the SIN1/SCK1/SIN2/SCK2 pins are used as input by the expanded I/O serial interface,
P90/SIN1, P92/SCK1, P40/SIN2, P42/SCK2 pins should be set to the input port by the port
direction register (DDR9 bit8, 10→"0" DDR4 bit0, 2→"0").
● Setting when using as SOT1/SOT2 pins
When the SOT1/SOT2 pins are used as the data output pin by the expanded I/O serial
interface, be sure to set the serial mode control status registers 0/1 (SMCS0/SMCS1) to enable
serial output (SOE bit1→"1").
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Block diagram of pin related to expanded I/O serial interface
Figure 18.2-2 Block diagram of pin related to expanded I/O serial interface
Port data register (PDR)
PDR Read
PDR Write
Port direction register (DDR)
DDR Write
DDR Read
Stand-by control: Stop mode (SPL=1), Timebase timer mode (SPL=1), Watch mode (SPL=1)
388
Peripheral function input
(SIN1/SIN2/SCK1/SCK2)
Output latch
Direction latch
Peripheral function
output (SOT1/SOT2)
Peripheral function output enable
Open drain control signal
Stand-by control (SPL=1)
(only P40/P41/P42)
P-ch
Pin
N-ch