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❍ External reset
An external reset is triggered by input of the "L" level to the external-reset pin (pin RST). More
than 16 machine cycles (16/φ) is required for the "L" level input time to pin RST.
An external reset (pin RST input reset) does not require the oscillation stabilization wait time.
Reference:
After an instruction processing ends, the reset cancellation waiting state is set only when a
reset request is issued via pin RST because of the event where a reset factor is triggered
during writing (such as the MOV instruction while a transfer instruction is being executed).
Writing thus ends normally even if a reset is input during writing.
However, string instructions (such as the MOVS instruction) accept a reset before a transfer
completes at the specified count, so the transfer of all data cannot be assured. Reset
requests are also accepted when a bus cycle extension with pin RDY continues for more
than 16 machine cycles during external bus access.
❍ Software reset
In a software reset, an internal reset is triggered by writing "0" in the internal reset signal bit
(RST) of the low-power consumption mode control register (LPMCR). A software reset does not
require the oscillation stabilization wait time.
Reference:
Definition of clock
HCLK: Oscillation clock (clock supplied via high-speed oscillation pin)
MCLK: Main clock (clock of HCLK divided by two)
SCLK: Sub-clock (clock divided by four, supplied via low-speed oscillation pin)
φ: Machine clock (CPU operation clock)
1/φ: Machine cycle (CPU operation clock period)
Refer to Section "5.1 Overview of Clocks", for a detailed information on machine clocks.
Note:
The oscillation stabilization wait time of 2
MHz) is required if a reset is triggered in the stop mode or the sub-clock mode.
Refer to Section "5.4 Clock Modes", for a detailed information on clock modes.
17
/HCLK (about 32.77 ms where the oscillation clock is 4
CHAPTER 4 RESET
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