Fujitsu MB90480 Series Hardware Manual page 674

Reload/compare register (ch0/ch1) (RCR0/1)
Selection of reload and compare functions
Up/down count at any width in reload/compare
............................................... 281
function
Condition code register
Condition code register (CCR)
Continuous mode
Example of μDMAC start in continuous mode
Control
Control status register 1 (ADCS1)
Control status register 2 (ADCS2)
Conversion data
Caution when using the conversion data protection
............................................... 376
function
Conversion data protection function
Operation flow of conversion data protection function
(when μDMAC is used)
Correspondence
Correspondence to DMA transfer and EI
............................................... 396
function
Count
Count clear/gate function
Count direction flag,count direction reversal flag
State transitions during count operation
Count clock
Count clock and maximum interval
........................................... 533
Count clock selection
....................................... 335
Selection of count clock
Count mode
....................................... 277
Selection of count mode
Counter
Block diagram of 8/16-bit up/down
........................................ 261
counter/timer
Block diagram of pin related to 8/16-bit up/down
........................................ 263
counter/timer
............................................ 283
Clearing the counter
Counter control register (ch0) upper (CCRH0)
Counter control register (ch0/ch1) lower
........................................... 269
(CCRL0/1)
Counter control register (ch1) upper (CCRH1)
Counter operation modes
Counter status register 0/1 (CSR0/1)
............................................... 72
Data counter (DCT)
Interrupt of 8/16-bit up/down counter/timer
Interrupt of 8/16-bit up/down counter/timer,DMA
2
transfer,and EI
Interrupt of PPG counter underflow
List of 8/16-bit up/down counter/timer registers
Major functions of 8/16-bit up/down
........................................ 260
counter/timer
Pin related to 8/16-bit up/down counter/timer
Program example of 8/16-bit up/down
........................................ 285
counter/timer
Counter operation
Measurement mode and counter operation
CPU
Connection between CPUs in master/slave
communication
652
............ 274
................ 280
................................. 33
........... 372
........................... 360
........................... 363
........................ 376
........................... 377
2
OS
...................................... 283
........ 284
.................... 305
......................... 538
........... 265
........... 267
...................................... 293
........................ 271
............... 275
................................. 276
OS
......................... 331
......... 264
............ 262
................ 541
...................................... 434
Connection between CPUs in two-way
communication
CPU intermittent operation mode
CPU operation mode and current consumption
Overview of the CPU specifications
CSCR
Chip selection control register (CSCR)
CSR
Counter status register 0/1 (CSR0/1)
D
Data
.............................................. 72
Data counter (DCT)
........................................... 571
Data register (IDAR)
Data registers (ADCR2 and ADCR1)
Data bus
Pin states in external bus 16-bit data bus mode and multiplex
16-bit external bus mode
Pin states in external bus 16-bit data bus mode and non-
multiplex 16-bit external bus mode
Pin states in external bus 8-bit data bus mode and non-
multiplex 8-bit external bus mode
Data counter
.............................................. 82
Data counter (DCT)
Data polling
State transitions of the data polling flag (DQ7)
DCT
........................................ 72, 82
Data counter (DCT)
DDR
Port direction registers (DDR0 to DDRA)
Delay
Block diagram of delay interrupt generation
.................................................. 93
module
List of registers in delay interrupt generation
.................................................. 93
module
Notes on using delay interrupt generation module
(delay interrupt request latch)
Operation of delay interrupt generation module
Detection
Setting Detection Address
Different mode
Setting bits of different modes (S1,S0)
Direct page
Direct page register (DPR)<Initial value: 01H>
Divide ratio
Divide ratio control register (DIVR0 to DIVR2)
DIVR
Divide ratio control register (DIVR0 to DIVR2)
DMA
Correspondence to DMA transfer and EI
........ 236, 276, 303, 332, 347, 367, 396,
422, 528, 573
DMA control status register (DMACS)
DMA descriptor configuration
DTP/external interrupt,DMA transfer,and EI
Interrupt of 16-bit input/output timer,DMA transfer,
2
............................................ 236
and EI OS
..................................... 432
................... 125, 131
.......... 124
.......................... 24
.................... 452
....................... 271
...................... 366
......................... 144
............ 146
.............. 147
.......... 489
................ 181
..................... 94
........... 94
.................................... 465
.................... 156
........... 38
........ 526
........ 526
2
OS function
...................... 73
................................. 70
2
....... 347
OS