Fujitsu MB90480 Series Hardware Manual page 140

F2mc-16lx 16-bit microcontroller
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CHAPTER 5 CLOCKS
❍ Change from the PLL clock mode to the sub-clock mode
Rewriting the sub-clock selection bit (SCS) of the clock selection register (CKSCR) from "1" to
"0" in the PLL clock mode changes the PLL clock to the sub-clock.
❍ Change from the sub-clock mode to the PLL clock mode
Rewriting the SCS bit in the CKSCR register from "0" to "1" in the sub-clock mode changes the
sub-clock to the PLL clock after the end of the oscillation stabilization wait time of the main
clock. Select the oscillation stabilization wait time by using selection bits (WS1, WS0) for the
oscillation stabilization wait time of the CKSCR register.
Note:
Rewriting the PLL clock selection bit (MCS) or SCS bit in the CKSCR register does not change the
machine clock immediately. When operating a resource that depends on a machine clock, make
sure that the intended machine clock change has completed by checking the PLL clock display bit
(MCM) and sub-clock display bit (SCM) in the CKSCR register. Then operate the resource.
If both of the SCS and MCS bits are "0", SCS is assigned with priority, and the sub-clock mode is
set.
When the clock mode is switched, do not switch to low-power consumption mode and other clock
mode before this switching is completed. Confirm the completion of clock mode switching by
referring to the MCM and SCM bits of the clock selection register (CKSCR). If the mode is switched
to another clock mode or low-power consumption mode before completion of switching, the mode
may not be switched.
Selection of PLL clock multiplication rate
If 00
to 11
B
multiply-by rates can be selected: multiply-by 1 to 4.
Machine clock
The PLL clock, main clock, and sub-clock output by the PLL multiplier circuit are machine
clocks, which are supplied to the CPU and peripheral functions. The main clock, PLL clock, and
sub-clock can be selected by writing in the SCS or MCS bit of the CKSCR register.
Figure 5.4-1 is a state transition diagram of machine clock selection.
118
are written to the CS1 and CS0 bits of the CKSCR register, four types of PLL clock
B

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