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CHAPTER 7 MODE SETTING
7.5.1
External memory access control signals
Access to external memory is performed in 3 cycles when the ready function is not
used.
■
External memory access control signal
Timing charts for external access in each mode are shown in Figure 7.5-1 to Figure 7.5-4.
Access with an 8-bit bus width in the 16-bit external data bus mode is a function for reading
from and writing to peripheral chips of an 8-bit width when a mixture of peripheral chips of an 8-
bit width and 16-bit width are connected to the external bus. Because access with an 8-bit bus
width is performed using the low-order 8 bits of the data bus, connect the peripheral chips of an
8-bit bus width to the low-order 8 bits of data. Access with either a 16-bit bus width or an 8-bit
bus width in the external data bus 16-bit mode is determined by the specification of the HMBS,
LMBS, and/or IOBS bit of EPCR. Incidentally, there is a case where bus operation is not
actually done by only outputting addresses and ALE assert results in the multiplex mode without
assert for RD, WRL, and WRH.
Note:
Be sure not to perform access to peripheral chips with only ALE signals.
❍ External data bus 8-bit mode (non-multiplex mode)
Figure 7.5-1 Access timing chart of external data bus 8-bit mode (non-multiplex mode)
P57/CLK
P53/WRH
P52/WRL
P51/RD
P50/ALE
A23 to 16
A15 to 08
A07 to 00
D15 to 08/
AD15 to 08
D07 to 00/
AD07 to 00
168
Read
(Port data)
Read address
Read address
Read address
(Port data)
Read data
Write
Write address
Write address
Write address
Write data
Read
Read address
Read address
Read address
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