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Table 6.7-1 Pin states in single chip mode is changed.
(*3: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output
Hi-Z" means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. →
143
*2: In the state of "Input cutoff", input A is masked and "L" level is transmitted internally. "Output Hi-Z"
means that the pin-drive transistors are disabled and the pins are set to the high-impedance state.)
Table 6.7-2 Pin states in external bus 16-bit data bus mode and multiplex 16-bit external bus mode is
changed.
(*6: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output
144
Hi-Z"means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. →
*5: In the state of "Input cutoff", input A is masked and "L" level is transmitted internally. "Output Hi-Z"
means that the pin-drive transistors are disabled and the pins are set to the high-impedance state.)
Table 6.7-3 Pin states in external bus 8-bit data bus mode and multiplex 8-bit external bus mode is changed.
(*6: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output
Hi-Z"means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. →
145
*5: In the state of "Input cutoff", input A is masked and "L" level is transmitted internally. "Output Hi-Z"
means that the pin-drive transistors are disabled and the pins are set to the high-impedance state.)
Table 6.7-4 Pin states in external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode is
changed.
(*6: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output
146
Hi-Z"means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. →
*5: In the state of "Input cutoff", input A is masked and "L" level is transmitted internally. "Output Hi-Z"
means that the pin-drive transistors are disabled and the pins are set to the high-impedance state.)
❍ Clearing of the watchdog timer is changed.
205
(Note: is changed.)
■ Compare clear register (CPCLR) is changed.
(When this register value matches the value of the 16-bit free-running timer, the 16-bit free-running timer
value is initialized to 0000
interrupt request is issued to the CPU. → When the MODE bit of the timer counter control status register
224
(TCCS) is set to "1", the freerunning timer value is initialized to "0000
the value of the free-running timer. When this register value matches the value of the free-running timer, a
compare clear interrupt flag is set. When the compare interrupt flag is set to "1", an interrupt request issues to
the CPU at allowing the interrupt operation.)
[bit3] SCLR is changed.
227
(Note: is added.)
Figure 12.3-8 Registers of output compare is changed.
229
(ICP1C → ICP1)
235
12.4 Interrupt of 16-bit Input/Output Timer is added.
246
12.6 Program Example of 16-bit Input/Output Timer is added.
275, 276
13.4 Interrupt of 8/16-bit Up/Down Counter/Timer is added.
285 to 290
13.6 Program Example of 8/16-bit Up/Down Counter/Timer is added.
[bit3] INTE (Timer interrupt request enable) is changed.
(Note: is added.)
299
[bit2] UF (Timer interrupt request flag) is changed.
(Note: is added.)
312 to 316
14.5 Program Example of 16-Bit Reload Timer is added.
Changes (For details, refer to main body.)
and a compare clear interrupt flag is set. When interrupt operation is allowed, an
H
xvi
" at matching this register value and
H
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