Interrupt Of 16-Bit Input/Output Timer - Fujitsu MB90480 Series Hardware Manual

12.4 Interrupt of 16-bit Input/Output Timer

The interrupt request of the 16-bit input/output timer occurs for three following.
• The counter value of the free-running timer overflows.
• The trigger edge input to the input capture input pin is performed.
• A match with the output compare is detected.
The DMA transfer and extended intelligent I/O service (EI
interrupt of the input capture and output compare.
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Interrupt of 16-bit input/output timer
Table 12.4-1 shows the interrupt control bit and interrupt source of the 16-bit input/output timer.
Table 12.4-1 Interrupt of 16-bit input/output timer
Interrupt request flag
Interrupt request output
enable bit
Interrupt generation
source
ICS01: ICP0/ICE0 correspond to input capture pin (IN0).
ICS01: ICP1/ICE1 correspond to input capture pin (IN0).
OCS01/23/45: ICP0/ICE0 correspond to output compare pins (OUT0/OUT2/OUT4).
OCS01/23/45: ICP1/ICE1 correspond to output compare pins (OUT1/OUT3/OUT5).
● Timer counter overflow interrupt
When the timer counter overflow interrupt request flag is set
The timer counter overflow generation flag in the timer counter control status register is set
when the followings occur (TCCS: IVF=1)
• When an overflow ("FFFF
• When the initialization by compare clear register is set to enable (TCCS: MODE=1) and an
match between the setting value of the free-running timer and the value of the compare clear
register occurs.
When the timer counter overflow interrupt request occurs
If the timer counter overflow interrupt request is set to enable (TCCS: IVFE=1), the interrupt
request is generated when the timer counter overflow generation flag is set to 1 (TCCS: IVF=1).
● Input capture interrupt
The interrupt operation when the valid edge (ICS: EG) set by the input capture pin is detected is
shown as follows :
• The count value of the free-running timer upon detection is stored in the input capture
register.
• The valid edge detection flag in the control status register is set to 1 (ICS: ICP=1).
• When the input capture interrupt request output is set to enable (ICS: ICE=1), the interrupt
Timer counter overflow interrupt
TCCS: IVF (bit7)
TCCS: IVFE (bit6)
Counter overflow of 16-bit
free-running timer
"→"0000
H
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
2
OS) can be activated for the
Input capture interrupt
ICS01: ICP1 (bit7) ch.1
ICS01: ICP0 (bit6) ch.0
ICS01: ICE1 (bit5) ch.1
ICS01: ICE0 (bit4) ch.0
Valid edge input to input
capture input pin
") occurs in counting up of the free-running timer
H
Output compare interrupt
OCS01/23/45: ICP1 (bit7) ch.1,3,5
OCS01/23/45: ICP0 (bit6) ch.0,2,4
OCS01/23/45: ICE1 (bit5) ch.1,3,5
OCS01/23/45: ICE0 (bit4) ch.0,2,4
Match between output compare
register value and counter value
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