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20.3.4 Chip Selection Active Level Register (CALR)
This section describes the configuration and functions of the chip selection active
level register (CALR).
■
Chip selection active level register (CALR)
The diagram below shows the bit configuration of the chip selection active level register (CALR).
15
0000C9
-
H
(-)
(-)
[bit15 to bit12] Unused bits
These bits are unused. In read operations, the return value for these bits is undefined.
[bit11 to bit8] ACTL3 to ACTL0
These bits set the active level of each CS3 to CS0 pin.
The followings are set.
•
"0": Each CS3 to CS0 pin outputs "L" after decoding.
•
"1": Each CS3 to CS0 pin outputs "H" after decoding.
Notes:
• Before changing the active level, prohibit output via the chip selection control register.
• Writing these bits in units of words is prohibited. Always write these bits in units of bytes. This will
prevent the enabling of output with the write operation at the same time that the active level is
changed.
14
13
12
11
-
-
-
ACTL3 ACTL2 ACTL1 ACTL0
(-)
(-)
(-)
(R/W) (R/W) (R/W) (R/W)
(-)
(-)
(-)
(0)
CHAPTER 20 CHIP SELECTION FACILITY
10
9
8
CALR
Chip selector active level register
Read/Write
(0)
(0)
(0)
Initial value
453
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