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CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER
● Method to clear up/down counter by ZIN pin
Set by the counter clear gate bit (CCR0.CGSC, CCR1.CGSC) and counter clear gate edge
selection bits (CCR0.CGE[1:0], CCR1.CGE[1:0]). (valid for all count modes).
To disable edge detection (no clear)
To clear up/down counter at falling edge
To clear up/down counter at rising edge
Setting GCE[1:0]=11 is prohibited
● Method to control up/down count operation by ZIN pin
Set by the counter clear gate bit (CCR0.CGSC, CCR1.CGSC) and counter clear gate edge
selection bits (CCR0.CGE[1:0], CCR1.CGE[1:0]). (valid for all count modes).
To operate up/down count at "L" level
and stop up/down count at "H" level
To stop up/down count at "L" level and
operate up/down count at "H" level
Setting GCE[1:0]=11 is prohibited
● Method to enable/disable count operation of up/down counter
Set by the count start bit (CSR0.CSTR, CSR1.CSTR) .
To disable count operation of up/down counter
To enable count operation of up/down counter
Starting counter is depending on the count mode.
Timer mode
Up/down count mode
Phase difference count mode → Start count upon detection of phase difference of AIN pin, BIN pin
However, it is necessary to detect the count operation enable level when the gate function of the ZIN pin
is selected.
288
ZIN pin input
ZIN pin input
To disable level detection
(count disabled state)
Operation
(for start)
→ Start count by internal clock
→ Start count upon detection edge of AIN pin, BIN pin
Counter clear gate bit
(CGSC)
Set to "0"
Set to "0"
Set to "0"
Counter clear gate bit
(CGSC)
Set to "1"
Set to "1"
Set to "1"
Count start bit (CSR0.CSTR, CSR1.CSTR)
Set to "0"
Set to "1"
Counter clear gate edge
selection bit (CGE[1:0])
Set to "00
"
B
Set to "01
"
B
Set to "10
"
B
Counter clear gate edge
selection bit (CGE[1:0])
Set to "00
"
B
Set to "01
"
B
Set to "10
"
B
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