Fujitsu MB90480 Series Hardware Manual page 252

CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
■
Output compare register (OCCP0 to OCCP5)
Output compare register (OCCP0 to OCCP5) has the bit configuration shown below.
Figure 12.3-9 Bit configuration of output compare register (OCCP0 to OCCP5)
ch.0
00004B
H
00004D
H
00004F
to
H C15
000051
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value
000053
H
ch.5
000055
H
00004A
ch.0
H
00004C
H
00004E
H
to C07
000050
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value
000052
H
ch.5
000054
H
R/W : Readable/Writable
The output compare register (OCCP0 to OCCP5) is a 16-bit length compare register used to
make a comparison with the free-running timer. This register is initialized at reset. This register
requires word access. If this register and the free-running timer have matching values, a
compare signal is generated to set the output compare interrupt flag. If output enable is given,
the output level corresponding to the compare register value is reversed and outputted.
■
Output compare control register (OCS01/OCS23/OCS45)
The output compare control register (OCS01/OCS23/OCS45) has the bit configuration shown
below.
Figure 12.3-10 Bit configuration of output compare control register (OCS01/23/45)
15
ch.0,1 000057
H
ch.2,3 000059
-
H
ch.4,5 00005B
H
(-)
7
ch.0,1 000056
H
ICP1 ICP0 ICE1 ICE0
ch.2,3 000058
H
ch.4,5 00005A
(R/W) (R/W) (R/W) (R/W)
H
R/W : Readable/Writable
- : Unused bit
The functions of the output compare control register bits (OCS01/OCS23/OCS45) are shown
below.
[bit15, bit14, bit13] Unused bits
These bits are not used. They are always set to "0".
[bit12] CMOD
This bit switches the pin output level reverse operation mode in compare result matching if
pin output is permitted (OTE1 = 1 or OTE0 = 1).
• If CMOD = 0 (initial value), the level corresponding to the compare register value is reversed.
- OUT0/2/4: Level is reversed if a match for compare register 0/2/4 is found
- OUT1/3/5: Level is reversed if a match for compare register 1/3/5 is found
230
15 14 13 12
C14 C13 C12
7 6 5 4
C06 C05 C04
14 13 12
- - CMOD OTE1 OTE0 OTD1 OTD0 Output compare control register
(-) (-) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value
6 5 4
11 10 9 8
C11 C10 C09 C08
3 2 1 0
C03 C02 C01 C00
11 10 9 8
3 2 1 0
- - CST1 CST0 Output compare control register
(-) (-) (R/W) (R/W) Initial value
OCCP0 to OCCP5
Output compare register
"00000000
OCCP0 to OCCP5
Output compare register
"00000000
OCS01/OCS23/OCS45
"- - -00000
B
OCS01/OCS23/OCS45
"0000- -00
B
"
B
"
B
"
"