Fujitsu MB90480 Series Hardware Manual page 73

F2mc-16lx 16-bit microcontroller
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Function of each bit in interrupt control register (ICR00 to ICR15)
❍ Interrupt level setting bit (IL2 to IL0)
This specifies the corresponding interrupt level in the peripheral function. A reset initializes the
bit to level 7 (no interrupts). Table 3.3-2 lists the relationship between interrupt level setting bits
and every interrupt level.
Table 3.3-2 Relationship between interrupt level setting bits and interrupt levels
IL2
0
0
0
0
1
1
1
1
❍ Extended intelligent I/O service (EI
When this bit is "1" at the generating interrupt request, EI
the generating interrupt request, the interruption sequence is started. When the EI
requirement is satisfied (without S1, S0=00
ISE bit with software when the corresponding resource doesn't have the EI
ISE bit is initialized to "0" by reset.
❍ Extended intelligent I/O service (EI
The ICS3 to ICS0 bits are write only bits and specify the channel of EI
determined depending on the value set to the ICS3 to ICS0 bits. The ICS3 to ICS0 bits are
initialized to "0000
Table 3.3-3 shows the relation between EI
Table 3.3-3 Relationship between EI
ICS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IL1
0
0
1
1
0
0
1
1
2
2
" by reset.
B
ICS2
ICS1
ICS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
IL0
Interrupt level
0
0 (Highest interrupt)
1
0
1
0
1
0
6 (Lowest interrupt)
1
7 (No interrupt)
OS) permission bit (ISE)
2
OS is started. When this bit is "0" at
), the ISE bit is cleared to "0". Please set "0" to the
B
OS) channel selection bit (ICS3 to ICS0)
2
OS channel selection bit and the descriptor address.
2
OS channel selection bits and descriptor address
Selected channel
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CHAPTER 3 INTERRUPT
2
OS end
2
OS function. The
2
OS descriptor address is
Descriptor address
000100
H
000108
H
000110
H
000118
H
000120
H
000128
H
000130
H
000138
H
000140
H
000148
H
000150
H
000158
H
000160
H
000168
H
000170
H
000178
H
51

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