Table of Contents
Advertisement
27.2
Configuration of I
■
Block diagram of the I
Figure 27.2-1 shows a block diagram of the I
CHAPTER 27 I
2
C Interface
2
C interface
Figure 27.2-1 Block Diagram of I
ICCR
EN
2
I
C enable
Clock divider 1
5
6
ICCR
CS4
Clock selector 1
CS3
Clock divider 2
CS2
2 4 8 16 32 64 128 256
CS1
CS0
Clock selector 2
IBSR
Bus busy
BB
Repeat start
RSC
Last bit
LRB
Transmit/
receive
TRX
FBT
AL
Arbitration lost detection
IBCR
BER
BEIE
Interrupt request
INTE
INT
IBCR
Start
SCC
Master
MSS
ACK permit
ACK
GC-ACK permit
GCAA
IBCR
Slave
AAS
Slave address
Global call
GCA
2
C INTERFACE (ONLY MB90485 SERIES)
2
C interface.
2
C Interface
Peripheral clock
7
8
Sync
Shift clock
edge change
timing
Start/stop
condition detection
Error
First byte
IRQ
End
Start/stop
condition generation
IDAR
compare
IADR
Shift clock generator
SCL
SDA
557
Advertisement
Table of Contents
