16-Bit Reload Timer Control Status Register (Upper) (Tmcsrhn) - Fujitsu MB95630H Series Hardware Manual

CHAPTER 20 16-BIT RELOAD TIMER
20.7 Registers
20.7.1 16-bit Reload Timer Control Status Register
(Upper) (TMCSRHn)
The 16-bit reload timer control status register (upper) (TMCSRHn) sets the
operating mode and operating conditions of the 16-bit reload timer.
■ Register Configuration
bit 7
Field —
Attribute —
Initial value 0
■ Register Functions
[bit7:6] Undefined bits
Their read values are always "0". Writing values to these bits has no effect on operation,
[bit5:3] CSL[2:0]: Count clock select bits
These bits select the count clock for the 16-bit reload timer.
When a value between "0b000" and "0b110" inclusive is written to these bits, the 16-bit reload timer counts
with the internal clock (internal clock mode). The internal clock is generated by the prescaler. For details, see
"3.9 Operation of Prescaler".
When "0b111" is written to these bits, the 16-bit reload timer counts with the edge of the external event clock
(event count mode).
bit5:3
Writing "000"
Writing "001"
Writing "010"
Writing "011"
Writing "100"
Writing "101"
Writing "110"
Writing "111"
*: MCLK: machine clock
F : main clock
CH
F : main CR PLL clock
MCRPLL
F : main CR clock
CRH
370
6 5
— CSL2
— R/W
0 0
Operating mode
Internal clock mode
Event count mode
FUJITSU SEMICONDUCTOR LIMITED
4 3
CSL1 CSL0
R/W R/W
0 0
Details
1 MCLK
MCLK/2
MCLK/4
MCLK/8
MCLK/16
MCLK/32
7
F /2 or F
CH
External clock
MB95630H Series
2 1
MOD2 MOD1
R/W R/W
0 0
Count clock*
6 6
/2 or F /2
CRH MCRPLL
MN702-00009-1v0-E
0
MOD0
R/W
0