Program Example Of 16-Bit Reload Timer - Fujitsu MB90480 Series Hardware Manual

CHAPTER 14 16-BIT RELOAD TIMER

14.5 Program Example of 16-Bit Reload Timer

This section explains the program example of the 16-bit reload timer.
■
Program example of 16-bit reload timer
Example of setting procedure
Software trigger output pulse from TOT0, duty1/2, normal
polarity
<Initial setting>
•
Setting
Set reload value
•
Control reload timer 0
Set control register
Select clock source>>
Select trigger>>
Enable output>>
Select output level>>
Select operation mode>>
Disable interrupt>>
Clear interrupt flag>>
Stop count>>
Software trigger>>
(no processing)
•
Interrupt related
Interrupt level of reload timer
Set I flag
<Start>
•
Start reload timer
Start PPG
Clear interrupt flag>>
Enable interrupt>>
Enable count>>
Software trigger (start)>>
<Interrupt>
•
Interrupt processing
(Arbitrary processing)
Clear interrupt request flag
Interrupt vector
•
Set vector table
Note:
Setting related to clock and setting of _set_il (numeric
value) are required in advance. See the chapter of
clock and interrupt.
312
Program example
void RT_sample(void)
{
RT_initial();
RT_start();
}
void RT_initial(void)
{
Register name. bit name
IO_TMRLR = 0xAA ;
TMRLR
TMCSR
IO_TMCSR.word = 0x0050; /* Setting value =0000_0000_0101_0000 */
.CSL1,CSL0
.MOD
.OUTE
.OUTL
.RELD
.INTE
.UF
.CNTE
.TRG
IO_ICR12.byte =0x10;
ICR12 __EI();
}
(CCR)
void RT_start(void)
{
Register name. bit name
IO_TMCSR.word = 0x005B;
TMCSR
UF
.INTE
.CNTE
.TRG
}
__interrupt void RT_int(void)
{
IO_TMCSR.bit.UF = 0;
........
TMCSR.UF
}
#pragma intvect RT_int 35
Note:
For the description form of the register, see "SAMPLE I/O REGISTER FILES FOR
2
F MC-16LX FAMILY MB90480 SERIES".
/* Insert any value for reload value */
/* bit15-12=0000 Undefined bit */
CSL1,CSL0 internal clock φ/2 */
/* bit11-10=00
/* bit9-7=000 MOD software trigger */
/* bit6=1 Enable OUTE output */
/* bit5=0 OUTL external output level Low */
/* bit4=1 Enable RELD reload */
/* bit3=0 Disable INTE interrupt */
/* bit2=0 Clear UF interrupt request flag */
/* bit1=0 Stop CNTE count */
/* bit0=0 TRG software trigger */
/* Set interrupt level */
/* Enable interrupt */
/* bit3=1 Enable INTE interrupt */
/* bit2=0 Clear UF interrupt request flag */
/* bit1=1 Start CNTE count */
/* bit0=1 TRG software trigger */
/* Interrupt occurs at generation of underflow */
/* bit2=0 Clear UF interrupt request flag */
/* Any processing operation */