Fujitsu MB90480 Series Hardware Manual page 683

PPG1/3/5 operation mode control register
......................................... 325
(PPGC1/3/5)
Program Address Detection Control Status Register
............................................. 461
(PACSR)
Program Address Detection Registers
(PADR0,PADR1)
Program counter bank register (PCB)<Initial value: value in
........................................... 37
reset vector>
PWC data buffer register (PWCR0 to PWCR 2)
Register settings in master/slave communication
Register settings in two-way communication
........................................... 179
Registers for I/O port
Registers of the ROM mirror function selection
................................................ 474
module
Reload registers (PRLL0 to PRLL5,
PRLH0 to PRLH5)
Reload/compare register (ch0/ch1) (RCR0/1)
Request level setting register (ELVR: External level
............................................... 345
register)
Serial control register (SCR)
Serial data register 0/1 (SDR0/SDR1)
Serial input/output register (SIDR/SODR)
Serial mode control status register0/1
........................................... 390
(SMCS0/1)
Serial mode register (SMR)
Serial status register (SSR)
Timebase timer control register (TBTC)
Timer control status register (TMCSR)
Timer counter control status register (TCCS)
Timer counter data register (TCDT)
Up/down count register (ch0/ch1) (UDCR0/1)
Up/down timer input enable register (UDER)
Watchdog timer control register (WDTC)
Register bank
Common register bank prefix (CMR)
General-purpose register (register bank)
Register bank pointer
Register bank pointer (RP)
Relationship
Relationship between mode pins and mode data (an example
showing recommended relationship)
Relationship between reload value and pulse
.................................................. 334
width
Reload
16-bit reload register (TMRLR)
16-bit timer register
(TMR)/16-bit reload register (TMRLR)
Operations of internal clock mode (reload mode)
Relationship between reload value and pulse
.................................................. 334
width
.................................................. 280
Reload function
........................................ 537
Reload operation mode
Reload registers (PRLL0 to PRLL5,
PRLH0 to PRLH5)
Reload/compare register (ch0/ch1) (RCR0/1)
Selection of reload and compare functions
Timer value and reload value
Up/down count at any width in reload/compare
............................................... 281
function
Reload register
Write timing to the reload register
.................................. 463
......... 525
........ 434
............. 432
................................. 330
............ 274
................................. 414
...................... 394
................ 416
................................... 412
.................................... 417
................... 190
.................... 297
............ 225
........................ 225
........... 273
............ 184
................. 201
........................ 41
..................... 39
...................................... 34
.......... 158
............................. 302
...... 301
....... 306
................................. 330
............ 274
................ 280
................................. 537
.......................... 337
Reload timer
Block diagram of pin related to 16-bit reload
...................................................295
timer
Block diagram of the 16-bit reload timer
Interrupt of 16-bit reload timer
Interrupt of 16-bit reload timer,DMA transfer,and
2
..................................................303
EI OS
Operation modes of the 16-bit reload timer
Pin related to 16-bit reload timer
Program example of 16-bit reload timer
Settings of the 16-bit reload timer
Repeated
One-Shot measurement and repeated
.........................................540
measurement
Request
External interrupt request level
Request level setting register (ELVR: External level
...............................................345
register)
Reset
Block diagram of external-reset pin
........................................105
Pin states during a reset
........................................................96
Reset factors
Reset factors and oscillation stabilization wait
......................................................98
time
Reset state waiting for stable oscillation
Setting the flash memory to the read/reset state
Reset-factor
Cautions about reset-factor bits
Correspondence between reset-factor bits and reset
.................................................104
factors
..................................................103
Reset-factor bits
Resetting
...........................................101
Overview of resetting
Resistor
Port input resistor registers (RDR0,RDR1)
Restart
..............................................................536
Restart
Result data
.......................................540
Measurement result data
ROM
Block diagram of the ROM mirror function selection
................................................474
module
Registers of the ROM mirror function selection
................................................474
module
ROMM (ROM mirror function selection
...............................................475
register)
ROMM
ROMM (ROM mirror function selection
...............................................475
register)
RP
Register bank pointer (RP)
S
S
Setting bits of different modes (S1,S0)
SCR
Serial control register (SCR)
...................294
...............................303
................292
.............................294
....................312
...........................304
...............................351
.........................100
.....................99
..........495
...............................104
................183
......................................34
.....................156
..................................414
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