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CHAPTER 19 UART
19.3.2 Serial Control Register (SCR)
This section describes the configuration and functions of the serial control register
(SCR).
■
Serial control register (SCR)
The bit configuration of the serial control register (SCR) is illustrated below.
15
000021
PEN
H
(R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) Read/write
(0)
The functions of the bits for the serial control register (SCR) are as follows:
[bit15] PEN: Parity ENable
This bit specifies whether to add a parity bit during transmission and to detect it during
receiving when processing serial data.
0
1
Note:
Parity can be added only in normal mode (Mode 0) in asynchronous (start-stop synchronization)
communication mode. Parity cannot be added in multiprocessor mode (Mode 1) or in CLK
synchronous communication (Mode 2).
[bit14] P: Parity
This bit specifies even or odd parity in data communications with parity.
0
1
[bit13] SBL: Stop Bit Length
This bit specifies the bit length of the stop bit, which is a frame end mark in asynchronous
(start-stop synchronization) communication.
0
1
414
14
13
12
11
P
SBL
CL
A/D
(0)
(0)
(0)
(0)
No parity
Parity provided
Even parity
Odd parity
1 stop bit
2 stop bits
10
9
8
REC RXE TXE
Serial control register (SCR)
(1)
(0)
(0)
Initial value
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