Fujitsu MB90480 Series Hardware Manual page 275

● Interrupt related register
The relationship between channel, interrupt level, and interrupt vector is shown in the following
table.
For details on the interrupt level and interrupt vector, see "CHAPTER 3 INTERRUPT".
Channel
Output compare 0
Output compare 1
Output compare 2
Output compare 3
Output compare 4
Output compare 5
Clear the interrupt request flag (OCS01.ICP[1:0], OCS23.ICP[1:0], OCS45.ICP[1:0]) by writing
"0" to ICP[1:0] bit with software before returning from the interrupt processing because the flag
is not cleared automatically.
● Type of interrupt
One interrupt is provided. Caused by a match of the comparison result.
● Method to enable interrupt
Enabling the interrupt is set by the interrupt request enable bit (OCS01.ICE[1:0], OCS23.ICE[1:0],
OCS45.ICE[1:0]).
Control
Disable interrupt
Enable interrupt
The interrupt request is cleared by the interrupt request bit (OCS01.ICP[1:0], OCS23.ICP[1:0],
OCS45.ICP[1:0]).
Control
Clear interrupt request
CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
Interrupt vector
#28
Address : FFFF8C
H
#29
Address : FFFF88
H
#30
Address : FFFF84
H
#31
Address : FFFF80
H
#32
Address : FFFF7C
H
#33
Address : FFFF78
H
Interrupt request enable bit (ICE0, ICE1)
Interrupt request bit (ICP0, ICP1)
Interrupt level setting register
Interrupt level register (ICR08)
Address : 0000B8
H
Interrupt level register (ICR09)
Address : 0000B9
H
Interrupt level register (ICR09)
Address : 0000B9
H
Interrupt level register (ICR10)
Address : 0000BA
H
Interrupt level register (ICR10)
Address : 0000BA
H
Interrupt level register (ICR11)
Address : 0000BB
H
Set to "0"
Set to "1"
Write "0"
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