Fujitsu MB90480 Series Hardware Manual page 612

F2mc-16lx 16-bit microcontroller

Table of Contents

Table C-1 Relationship between interrupt sources and interrupt vector/interrupt control registers (2/2)

Interrupt source

Input capture (ch.1) load

Output compare (ch.0) match

Output compare (ch.1) match

Output compare (ch.2) match

Output compare (ch.3) match

Output compare (ch.4) match

Output compare (ch.5) match

UART transmit completed

16-bit free-run timer/16-bit reload

timer overflow *

UART receive completed

(only MB90485 series)

A/D converter

FLASH write/delete, timebase timer/

watch timer *

Delay interrupt generate module

×: The interrupt request can not be cleared by the interrupt clear signal.

❍: The interrupt request can be cleared by the interrupt clear signal.

:The interrupt request can be cleared by the interrupt clear signal. With a stop request.

*1: Make sure that flash write/delete operations are not used during operation of the timebase timer and watch

*2: When the reload timer underflow interrupt is changed from enabled (INTE bit of TMCSR register = 1) to

disabled (INTE bit of TMCSR register = 0), "0" is written to the INTE bit after the IL2 to IL0 bits of the

interrupt control register (ICR12) is set to "111

If the same interrupt number is assigned to two interrupt sources, the resource is cleared only if both

interrupt request flags are cleared. Therefore, if either of two interrupt functions uses the EI

function or μDMAC function, the other interrupt function cannot be used. Set the relevant resource's

interrupt request enable bit to "0" and use software polling processing to handle this situation.

Interrupt vector

" to disable the interrupt.

Interrupt control