Interrupt Of 8/16-Bit Ppg Timer - Fujitsu MB90480 Series Hardware Manual

15.4

Interrupt of 8/16-Bit PPG Timer

The interrupt of the 8/16-bit PPG timer occurs when the PPG counter underflow is
detected.
The interrupt of the PPG counter underflow cannot activate the DMA transfer and
extended intelligent I/O service (EI
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Interrupt of 8/16-bit PPG timer
Table 15.4-1 shows the interrupt control bit and interrupt source of the 8/16-bit PPG timer.
Table 15.4-1 Interrupt of 8/16-bit input/output timer
Interrupt request flag
Interrupt request
output enable bit
Interrupt generation
source
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Interrupt of PPG counter underflow
● 8-bit PPG and 8 + 8-bit PPG output operation mode
• In the 8-bit PPG 6-channel independent operation mode or the 8 + 8-bit PPG output
operation mode, the interrupt can be generated independently.
• When the value of the PPG down counter is decremented from "00
occurs. When an underflow occurs, the underflow bit in the channel causing an underflow is
set (PUF0 = 1, PUF1 = 1).
● 16-bit PPG output operation mode
• In the 16-bit PPG output operation mode, when the values of the PPG0 + PPG1/PPG2 +
PPG3/PPG4 + PPG5 down counters are decremented from "0000
occurs. When an underflow occurs, the underflow generation bits in the two channels are set
at one time (PIF0 = 1, PIF1 = 1).
• When an underflow occurs with either of the two channels of the interrupt requests enabled
(PIE0 = 0 + PIE1 = 1, PIE0 = 1 + PIE1 = 0), an interrupt is generated.
• To prevent duplication of interrupt requests, disable either of the two channels of the
underflow interrupt enable bits (PIE0 = 0 + PIE1 = 1, PIE0 = 1 + PIE1 = 0).
• When the two channels of the underflow generation flag bits are set (PUF0 = 1, PUF1 = 1),
clear the two channels at the same time.
2
OS).
PPG0/2/4 overflow interrupt
PPG0:PUF0 (bit3) ch.0
PPG2:PUF0 (bit3) ch.2
PPG4:PUF0 (bit3) ch.4
PPG0:PUE0 (bit4) ch.0
PPG2:PUE0 (bit4) ch.2
PPG4:PUE0 (bit4) ch.4
Overflow in PPG0/PPG2/PPG4 down
counter
CHAPTER 15 8/16-BIT PPG TIMER
PPG1/3/5 overflow interrupt
PPG1:PUF1 (bit3) ch.1
PPG3:PUF1 (bit3) ch.3
PPG5:PUF1 (bit3)
PPG1:PUE1 (bit4) ch.1
PPG3:PUE1 (bit4) ch.3
PPG5:PUE1 (bit4)
Overflow in PPG1/PPG3/PPG5 down
counter
" to "FF ", an underflow
H H
" to "FFFF ", an underflow
H H
ch.5
ch.5
331