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CHAPTER 2 CPU
❍ Z: Zero flag
If all operation results indicate "0", the Z-flag is set. Otherwise, it is cleared.
❍ V: Overflow flag
If an overflow with a signed figure occurs as an operation execution result, the V-flag is set.
Otherwise, it is cleared.
❍ C: Carry flag
If a shift-in/shift-out operation occurs from MSB as operation execution results, the C-flag is set.
Otherwise, it is cleared.
■
Register bank pointer (RP)
The register bank pointer (RP) shows the relationship between the F
register and internal RAM addresses. RP indicates the header memory address in the currently
used register bank with the conversion formula [00180
RP consists of 5 bits, with an address ranging from 00
A register bank can be allocated to a memory address in a range of 000180
in this range, however, a register bank cannot be used as a general-purpose register if a
register bank is not in internal RAM. An instruction transfers an immediate value of 8 bits to RP,
but only the lower 5 bits are actually used.
■
Interrupt level mask register (ILM)
The interrupt level mask register (ILM) consists of 3 bits indicating the level of the CPU interrupt
mask. Only interrupt request of an interrupt level higher than that represented with the 3 bits is
accepted. The highest level is indicated with "0", the lowest level is indicated with "7" (see Table
2.3-1). Thus, to accept an interrupt, its level must be lower than the current ILM value. If an
interrupt is accepted, its interrupt level value is set to ILM, and then any interrupts with the same
or lower level of the interrupt priority are not accepted. ILM is initialized to zero by a reset. An
instruction can transfer an 8-bit immediate value to the ILM register, but only the lower 3 bits are
actually used.
Figure 2.3-9 shows the configuration of the interrupt level mask register. Table 2.3-1 has
explanations of the level indicated in the interrupt level mask register (ILM).
34
Figure 2.3-8 Configuration of register bank pointer (RP)
B4
0
Initial value
Figure 2.3-9 Configuration of interrupt level mask register
Initial value
+ RP x 10
H
to 1F
.
H
H
B3
B2
B1
B0
0
0
0
0
ILM2
ILM1
ILM0
0
0
0
2
MC-16LX general-purpose
].
H
to 00037F
. Even
H
H
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