Bus Status Register (Ibsr) - Fujitsu MB90480 Series Hardware Manual

2
CHAPTER 27 I C INTERFACE (ONLY MB90485 SERIES)

27.3.1 Bus Status Register (IBSR)

This section describes the configuration and functions of the bus status register
(IBSR).
■
Bus status register (IBSR)
The diagram below shows the bit configuration of the bus status register (IBSR).
The functions of bits in the bus status register (IBSR) are described below.
[bit7] BB: Bus Busy
This bit is used to indicate the I
0
1
[bit6] RSC: Repeated Start Condition
This bit is used to detect a repeated start condition.
0
1
This bit is cleared by setting the INT bit to "0" for addressing in a mode other than slave
mode if a start condition is detected in bus idle state or if a stop condition is detected.
[bit5] AL: Arbitration Lost
This bit is used to detect the arbitration lost state.
0
1
Cleared if the INT bit is set to "0".
[bit4] LRB: Last Received bit
This bit is an acknowledge storage bit used to store an acknowledgement from the reception side.
0
1
560
Bus status register
7
Address: 000088
H
BB RSC AL
Read/Write
(R)
Initial value
(0)
Stop condition is detected.
Start condition is detected (bus is used).
Repeated start condition is not detected.
Start condition is detected again when bus is used.
Arbitration lost is not detected.
Arbitration lost is generated in master transfer mode, or the MSS bit is set to "1" while
another system is using the bus.
Reception is acknowledged.
Reception is not acknowledged.
6 5 4 3
LRB TRX AAS GCA FBT
(R) (R) (R) (R)
(0) (0) (0) (0)
2
C bus status.
2 1 0 Bit number
IBSR
(R) (R) (R)
(0) (0) (0)