Μdmac Processing Time - Fujitsu MB90480 Series Hardware Manual

CHAPTER 3 INTERRUPT
μDMAC Processing Time
3.6.4
Time consumed in μDMAC processing varies with the following factors:
• Settings of DMA control status register (DMACS)
• Address (area) indicated by the I/O register address pointer (IOA)
• Address (area) indicated by the buffer address pointer (BAP)
• External data bus width for external access
• Data length of transfer data
When the μDMAC data transfer ends, a hardware interrupt starts, and then the
interrupt processing time is added.
μDMAC processing time (time per one-time transfer)
■
❍ If data transfer continues
The μDMAC processing time during a continuation of a data transfer depends on the setting of
DMA control status register (DMACS), as shown in Table 3.6-2.
Table 3.6-2 μDMAC execution time
Setting of IOA update/fixed selection bit (IF)
BAP address update/fixed
Setting of selection bit (BF)
Note:
In units of machine cycles. One machine cycle corresponds to one clock interval of the machine
clock (φ).
Correction is required depending on the condition at μDMAC execution, as shown in Table 3.6-
3.
Table 3.6-3 Correction values of data transfer for μDMAC execution time
Buffer address
pointer
76
I/O register address pointer
Internal access
External access
Fixed
Update
Internal access
B/even Odd
B/even 0 +2
Odd +2 +4
B/even +1 +3
8/odd +4 +6
Fixed Update
17 19
19 21
External access
B/even 8/odd
+1 +4
+3 +6
+2 +5
+5 +8