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CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES)
25.3.3 Divide Ratio Control Register (DIVR0 to DIVR2)
This section describes the configuration and functions of the divide ratio control
register (DIVR0 to 2).
■
Divide ratio control register (DIVR0 to DIVR2)
Figure 25.3-4 shows the bit configuration of the divide ratio control register (DIVR0 to DIVR2).
Figure 25.3-4 Bit configuration of the divide ratio control register (DIVR0 to DIVR2)
7
ch.0 000082
H
ch.1 000084
H
ch.2 000086
H
(-)
(-)
This register is only used in divide interval measurement mode (PWCSR: bit2, bit1, bit0:MOD2,
MOD1, MOD0 = 001
In divide interval measurement mode, pulses input to the measurement pin are divided
according to the divide ratio set in this register. This allows measuring one interval width.
Table 25.3-7 Selection of divide ratio
DIV1
0
0
1
1
•
Initialized to "00
•
Reading and writing are allowed.
Note:
Rewriting after timer start is prohibited. Write always either before the timer is started or after it is
stopped.
526
6
5
4
-
-
-
-
(-)
(-)
(-)
(-)
(-)
(-)
); it is not used in other modes.
B
DIV0
0
Divide-by-4 [initial value]
1
Divide-by-16
0
Divide-by-64
1
Divide-by-256
" at reset
B
3
2
1
0
-
-
DIV1 DIV0
(-)
(-)
(R/W) (R/W)
(-)
(-)
(0)
(0)
Count clock selection
DIVR
Divide ratio control register
Read/write
Initial value
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