Fujitsu MB90480 Series Hardware Manual page 135

Note:
When reset, the machine clock selection (MCS) bit is initialized to the main clock selection.
Table 5.3-1 Functions of bits in clock selection register (CKSCR) (1/2)
Bit name
SCM:
bit15
Sub-clock display bit
MCM:
bit14
PLL clock display bit
WS1, WS0:
bit13
Oscillation stabilization
bit12
wait time selection bits
This bit displays whether the main clock or sub-clock is selected as a
machine clock.
• If the bit is "0", the sub-clock is selected. If "1", the main clock or PLL
clock is selected.
• If SCS = 1 and SCM = 0, the mode is the waiting time for stable
oscillation of the main clock.
• Write doesn't affect operation.
This bit displays whether the main clock or PLL clock is selected as a
machine clock.
• If this bit is "0", the PLL clock is selected. If "1", the main clock or sub-
clock is selected.
• If PLL clock selection bit (MCS) = 0 and MCM = 1, the mode is the
waiting time for stable oscillation of the PLL clock.
• Write doesn't affect operation.
Selects the waiting time for stable oscillation of oscillation clock in a
change from the sub-clock mode to the main clock mode or from the
sub-clock mode to the PLL clock mode if the stop mode is canceled.
Initialized to "11 " by all reset factors.
B
Note:
The specified value of the waiting time for stable oscillation must be
suitable for the oscillator used. Refer to Section "4.2 Reset Factors
and Oscillation Stabilization Wait Time", for more information. Specify
"00 " only if the mode is the main clock mode.
B
When the main clock is switched to PLL clock mode, the PLL clock
oscillation stabilization wait time is fixed at 2
When sub-clock mode is switched to PLL clock mode or when PLL
stop mode is returned to PLL clock mode, the oscillation stabilization
wait time uses the specified values in the WS1 and WS0 bits. For PLL
clock oscillation stabilization wait time, at least 2
Accordingly, when sub-clock mode is switched to PLL clock mode, or
when PLL clock mode is switched to PLL stop mode, set WS1 and
WS0 bits to "10 " or "11
B
Function
14
/HCLK.
14
".
B
CHAPTER 5 CLOCKS
/HCLK is required.
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