Fujitsu MB90480 Series Hardware Manual page 99

Note:
B indicates a byte data transfer, 8 indicates a word transfer with an external bus width of 8 bits,
even indicates word transfer of an even-numbered address, and odd indicates a word transfer of
an odd-numbered address.
❍ Transfer performance
Minimum transfer speed
1.7 μs/10 MHz (machine clock)
1.07 μs/16 MHz (machine clock)
Built-in I/O → built-in RAM; or built-in RAM → built-in I/O without address increment
•
Even-numbered address → even-numbered address or 8-bit access
•
Maximum transfer speed
2.8 μs/10 MHz (machine clock)
1.75 μs/16 MHz (machine clock)
Table 3.6-4 indicates the correction values for interrupt handling time.
Table 3.6-4 Correction values (Z) for interrupt handling time
External 8 bits
External even-numbered address
External odd-numbered address
Internal even-numbered address
Internal odd-numbered address
❍ If a transfer is ended with an end request from a peripheral function (I/O)
If the μDMAC data transfer ends partway (DEx = 1) because of an end request by a peripheral
function (I/O), the data transfer fails and a hardware interrupt starts. The μDMAC processing
time in this case is calculated with the following formula. Z in the formula indicates a correction
value for interrupt processing time (see Table 3.6-4).
The μDMAC processing time if a transfer ends partway is:
36 + 6 × Z machine cycle
where one machine cycle corresponds to one clock interval of the machine clock (φ).
Address indicated by stack pointer
CHAPTER 3 INTERRUPT
Correction value (Z)
+4
+1
+4
0
+2
77