State Transition Diagram - Fujitsu MB90480 Series Hardware Manual

6.6

State Transition Diagram

This section explains the transition of operational states for the MB90480/485 series
and describes the transition conditions.
■
State transition diagram
Figure 6.6-1 illustrates the transition of operational states for the MB90480/485 series and the
transition conditions.
External reset, watchdog timer reset, software reset
Power on
Power-on reset
End of oscillation
stabilization wait
Main clock mode
SLP=1
Main sleep mode
TMD=0
Main timebase
timer mode
STP=1
Main stop mode
Interrupt
Oscillation
stabilization wait
of main clock
Figure 6.6-1 State transition and transition conditions
Reset
SCS=1
MCS=0
PLL clock mode
MCS=1
SLP=1
Interrupt
PLL sleep mode
TMD=0
Interrupt
PLL timebase
STP=1
PLL stop mode
End of oscillation
Interrupt
stabilization wait
stabilization wait
CHAPTER 6 LOW-POWER CONSUMPTION MODE
SCS=0
SCS=0
SCS=1
Interrupt
Interrupt
timer mode
End of oscillation
stabilization wait
Oscillation
of main clock
Sub-clock mode
SLP=1
Interrupt
Sub sleep mode
TMD=0
Interrupt
Watch mode
STP=1
Sub stop mode
End of oscillation
Interrupt
stabilization wait
Oscillation
stabilization wait
of sub-clock
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