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CHAPTER 10 WATCHDOG TIMER
10.1 Overview of Watchdog Timer
The watchdog timer is a 2-bit counter that uses the output of the timebase timer or the
watch timer as the count clock, and if it is not cleared within a certain period of time
after startup, this timer resets the CPU.
■
Functions of watchdog timer
The watchdog timer is a counter used to prevent runaway programs. Once it is started, this
timer must be cleared periodically within a certain period of time. If it is not cleared within a
certain period of time because a program is running in an infinite loop, it generates a watchdog
reset to the CPU. The interval time of the watchdog timer can be specified on the WT1 and WT0
bits in the watchdog timer control register (WDTC), as shown in Table 10.1-1. If the watchdog
timer is not cleared, a watchdog reset is generated between the minimum time and the
maximum time. Be sure to clear the timer within the minimum time.
The output destination of the clock source is set by the watchdog clock selection bit
(WTC:WDCS) of the clock timer control register.
Table 10.1-1 Interval time for watchdog timer
WT1
WT0
WDCS
0
0
1
0
1
1
1
0
1
1
1
1
0
0
Combination
0
1
other than the
1
0
above
1
1
*: Values during operation of the oscillation clock (HCLK) at 4 MHz and the sub-clock (SCLK) at 32 kHz frequency divided
by 4 (= 8 kHz)
The maximum and minimum watchdog timer interval times and the number of the oscillation clock cycles depend on the
timing of the clear operation. The interval time is 3.5 to 4.5 times as large as the cycle of the count clock (clock supplied
by the timebase timer).
For the watchdog timer interval times, see Section "10.4 Watchdog Timer Operation".
Note:
The watchdog counter is composed of a 2-bit counter to count the carry signals of the timebase
timer. Therefore, if the timebase timer counter has been cleared, the time until the occurrence of
watchdog reset may become longer than the specified time.
To use the sub-clock as a machine clock, please select the output of the clock timer by setting the
watchdog timer clock source selection bit (WDCS) of the clock timer control register (WTC) to "0".
200
SCM
Minimum *
1
Approximately 3.58 ms
1
Approximately 14.33 ms
1
Approximately 57.23 ms
1
Approximately 458.75 ms
Approximately 0.457 s
Approximately 3.584 s
Approximately 7.168 s
Approximately 14.336 s
Interval time
Maximum *
Approximately 4.61 ms
Approximately 18.43 ms
Approximately 73.73 ms
Approximately 589.82 ms
Approximately 0.576 s
Approximately 4.608 s
Approximately 9.216 s
Approximately 18.432 s
Number of clock
cycles
±
14
11
(2
2
)/HCLK cycles
±
16
13
(2
2
)/HCLK cycles
±
18
15
(2
2
)/HCLK cycles
±
21
18
(2
2
)/HCLK cycles
±
12
9
(2
2
)/SCLK cycles
±
15
12
(2
2
)/SCLK cycles
±
16
13
(2
2
)/SCLK cycles
±
17
14
(2
2
)/SCLK cycles
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