Fujitsu MB90480 Series Hardware Manual page 216

CHAPTER 9 TIMEBASE TIMER
Table 9.5-1 Timebase timer counter clear operation and oscillation stabilization wait
time.
Writing "0" to timebase timer
initializing bit (TBR) for
timebase timer control
register (TBTC)
Power-on reset
Watchdog reset
Release of the main stop
mode
Release of the PLL stop
mode
Release of the sub stop
mode
Switching from main clock
mode to PLL clock mode
(SCM: transition from 1 to 0)
Transition from sub-clock
mode to main clock mode
(SCM: transition from 0 to 1)
Release of timebase timer
mode
Release of sleep mode
: Cleared
✕: Not cleared
■
Clock supplying function
The timebase timer supplies a clock to the watchdog timer. Clearing of the timebase timer
counter affects the operation of the watchdog timer.
194
Counter
Operation
TBOF
Oscillation stabilization wait time
clear clear
✕
Oscillation stabilization wait time of
main clock
Oscillation stabilization wait time of
✕ ✕
sub-clock
Oscillation stabilization wait time of
PLL clock
Oscillation stabilization wait time of
main clock
✕ ✕
✕ ✕