Fujitsu MB90480 Series Hardware Manual page 270

CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
• Reset
The free-running timer is cleared by reset (external reset, watchdog reset, software reset).
• Set "0000
When "0000
free-running timer is stopped, the count value is cleared to "0000
● Interrupt related register
The relationship between the interrupt level and interrupt vector is shown in the following table.
For details on the interrupt level and interrupt vector, see "CHAPTER 3 INTERRUPT".
Address : FFFF70
Clear the interrupt request flag (TCCS.IVF) with software before returning from the interrupt
processing because the flag is not cleared automatically (write "0" to IVF bit).
● Type of interrupt
One interrupt is provided only. Caused by overflow of the free-running timer.
● Method to enable interrupt
Enabling/disabling interrupt sets using the interrupt request enable bit (TCCS.IVFE).
Disable interrupt
Clearing the interrupt request sets using the interrupt request bit (TCCS.IVF).
Clear interrupt request
● Method to stop operation of free-running timer
Set by count operation bit (TCCS.STOP).
To stop count operation of free-running
248
" to timer counter data register (TCDT)
H
" is written to the timer counter data register (TCDT) during operation of the
H
Interrupt vector
#35
H
Control
Enable interrupt
Control
Operation
".
H
Interrupt level setting register
Interrupt level register (ICR12)
Address : 0000BC
Interrupt request enable bit (IVFE)
Set to "0"
Set to "1"
Interrupt request bit (IVF)
Write "0"
Count operation bit (STOP)
Set to "1"
H