Fujitsu MB90480 Series Hardware Manual page 424

F2mc-16lx 16-bit microcontroller

Table of Contents

CHAPTER 18 EXPANDED I/O SERIAL INTERFACE

❍ Instruction shift in external shift clock mode (LSB first)

During instruction shift, "H" will be output if the bit corresponding to SCK in PDR is set to "1" and

"L" will be output if the bit is set to "0". (If SCOE = 0 when external shift clock mode is selected.)

❍ Stop by STOP = 1 (LSB first, internal clock used)

Operation during serial data transfer

During serial data transfer, data from the serial output pin (SOT2) is output at a falling edge of

the shift clock. Data from the serial input pin (SIN) is input at a rising edge.

❍ LSB first (if the BDS bit is "0")

❍ MSB first (If the BDS bit is "1")

Figure 18.5-5 Instruction shift in external shift clock mode

PDR SCK bit "0"

Figure 18.5-6 Stop timing when the STOP bit is set to "1"

(Transfer start)

Figure 18.5-7 Input and output shift timing (LSB first)

Figure 18.5-8 Input and output shift timing (MSB first)

PDR SCK bit "1"

(Transfer end)

DO5 (Data hold)

PDR SCK bit "0"

DO7 (Data hold)

Output of "1"