Fujitsu MB90480 Series Hardware Manual page 675

Interrupt of 16-bit reload timer,DMA transfer,and
2
................................................. 303
EI OS
Interrupt of 8/10-bit A/D converter,DMA transfer,and
2
................................................. 367
EI OS
Interrupt of 8/16-bit PPG timer,DMA transfer,
2
............................................ 332
and EI OS
Interrupt of 8/16-bit up/down counter/timer,DMA
2
transfer,and EI
Interrupt of expanded I/O serial interface,DMA transfer,
2
............................................ 396
and EI OS
2
Interrupt of I C interface,DMA transfer,
2
............................................ 573
and EI OS
Interrupt of PWC timer,DMA transfer
2
........................................... 528
,and EI OS
Interrupt of UART,DMA transfer,and EI
DMACS
DMA control status register (DMACS)
DPR
Direct page register (DPR)<Initial value: 01H>
DQ
State transitions of sector erase timer flag (DQ3)
State transitions of the data polling flag (DQ7)
State transitions of the timing limit excess flag
................................................. 492
(DQ5)
State transitions of the toggle bit flag (DQ6)
DTB
Bank select prefix (PCB,DTB,ADB,SPB)
DTP
Block diagram of DTP/external interrupt unit
Block diagram of pin related to DTP/external
.............................................. 343
interrupt
................................................... 349
DTP operation
........................................ 346
DTP/External Interrupt
DTP/external interrupt,DMA transfer,and EI
Interrupt/DTP enable register (ENIR: Enable interrupt
request register)
Interrupt/DTP source register (EIRR: External interrupt
request register)
List of registers for DTP/external interrupt unit
Overview of DTP/external interrupt unit
Pin related to DTP/external interrupt
Procedures for DTP/external interrupt unit
............................................. 350
operation
Program Example of DTP/External Interrupt
E
2
E PROM
2
....................................... 467
E PROM Memory Map
Operation of Address Match Detection Function at Storing
Patch Program in E
System Configuration and E
.................................................... 466
Map
2
EI OS
2
Configuration of EI OS Descriptor (ISD)
Correspondence to DMA transfer and EI
......... 236, 276, 303, 332, 347, 367, 396,
422, 528, 573
DTP/external interrupt,DMA transfer,and EI
2
EI OS Status Register (ISCS)
................................. 276
OS
2
............ 422
OS
...................... 73
........... 38
........ 493
.......... 489
............. 491
.................. 40
............ 342
2
....... 347
OS
.................................... 344
..................................... 345
.......... 344
.................. 342
....................... 342
............. 352
2
...................... 469
PROM
2
PROM Memory
................... 80
2
OS function
2
....... 347
OS
.................................. 83
Extended intelligent I/O service (EI
Flowchart of Operation of EI
Interrupt of 16-bit input/output timer,DMA transfer,
2
............................................236
and EI OS
Interrupt of 16-bit reload timer,DMA transfer, and
2
..................................................303
EI OS
Interrupt of 8/10-bit A/D converter,DMA transfer,
2
............................................367
and EI OS
Interrupt of 8/16-bit PPG timer,DMA transfer, and
2
..................................................332
EI OS
Interrupt of 8/16-bit up/down counter/timer,DMA
transfer, and EI
Interrupt of expanded I/O serial interface,DMA transfer, and
2
..................................................396
EI OS
2
Interrupt of I C interface,DMA transfer, and EI
Interrupt of PWC timer,DMA transfer, and EI
Interrupt of UART,DMA transfer,and EI
2
...............................................79
Operation of EI OS
2
Procedure for Use of EI OS
Processing time (one transfer time) of the extended
intelligent I/O service (EI
EIRR
Interrupt/DTP source register (EIRR: External interrupt
request register)
ELVR
Request level setting register (ELVR: External level
...............................................345
register)
ENIR
Interrupt/DTP enable register (ENIR: Enable interrupt
request register)
EPCR
Bus control signal selection register (EPCR)
Erase
Flash memory write/erase
Erasing
Erasing all data in the flash memory (chip erase)
Erasing arbitrary data in the flash memory
.........................................499
(sector erase)
Methods for writing/erasing flash memory
Error
...........................................................575
Bus error
Event
Event count mode (external clock mode)
Operation in event count mode
Execution Cycle
Calculating the Execution Cycle Count
.........................................606
Execution Cycle Count
Extended intelligent I/O service
Extended intelligent I/O service (EI
Processing time (one transfer time) of the extended
intelligent I/O service (EI
External address
External address output control register (HACR)
External bus
Pin states in external bus 16-bit data bus mode and
multiplex 16-bit external bus mode
Pin states in external bus 16-bit data bus mode and
non-multiplex 16-bit external bus mode
2
....................78
OS)
2
..............................85
OS
2
.................................276
OS
2
....573
OS
2
......528
OS
2
.............422
OS
.....................................86
2
.....................87
OS)
.....................................345
....................................344
..............165
......................................494
........498
................478
..................292
...............................310
....................607
2
....................78
OS)
2
.....................87
OS)
........164
.............144
.......146
653