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CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION
■
Flow of Patch Processing
Figure 21.4-5 shows the flow of patch processing.
000000
000100
000400
000480
000900
FF0000
FF8000
FF8050
FFFFFF
470
Figure 21.4-5 Flow of Patch Processing
MB90480/485 series
I/O area
H
Register/RAM area
H
Patch program
H
RAM area
H
Stack area
Program address detection register
H
H
Program error
H
H
H
Reset
Read the 00
2
of E
PROM
YES
2
E
PROM : 0000
= 0
NO
Read detection address
2
E
PROM : 0001
H
↓ MOV
MCU : Set to PADR0
Read patch program
2
E
PROM : 0010
H
↓
MCU : 000400
to 00047F
H
Enable address match detection
(PACSR : AD0E = 1)
Execution of normal
program
NO
Program address
PC = PADR0
0000
0001
0002
0003
RAM
0010
0090
FFFF
ROM
H
H
to 0003
H
to 008F
H
H
YES
INT9
2
E
PROM
Patch program byte count : 80
H
Detect address (Low) : 00
H
Detect address (Middle) : 80
H
Detect address (High) : FF
H
Patch program
H
H
H
INT9
Branch to patch program
JMP 000400
H
Execution of patch program
000400
to 000480
H
H
End of patch program
JMP FF8050
H
H
H
H
H
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