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Interrupt by μDMAC
3.6
The μDMAC controller is a simplified DMA that has the same function as EI
transfers are set up using the DMA descriptor.
μDMAC functions
■
μDMAC has the functions listed below.
•
Provides an automatic data transfer between a peripheral resource (I/O) and memory.
•
CPU program execution stops during the DMA start sequence.
•
The DMA transfer channel has 16 channels (a smaller channel number is assigned a higher
DMA transfer priority)
•
Allow selection of whether or not to increment the transfer source and transfer destination
addresses.
•
The DMA transfer starts with an interrupt factor of the peripheral resource (I/O).
DMA transfers are controlled with the (a) μDMAC enable register, (b) μDMAC stop status
•
register, (c) μDMAC status register and (e) descriptor (assigned to a range of 000100
00017F
•
STOP requests are issued as a means to stop DMA transfers from a resource.
•
After the end of the DMA transfer, a flag is set to the bit corresponding to the transfer end
channel of the DMA status register, and an end interrupt is then output to the interrupt
controller.
List of μDMAC registers
■
❍ μDMAC enable register (DER)
μDMAC enable register (DER) has the bit configuration shown in the diagram below.
bit
15
0000AD
EN15
R/W
7
0000AC
EN7
R/W
in RAM).
H
14
13
12
EN14
EN13
EN12
EN11
R/W
R/W
R/W
R/W
6
5
4
EN6
EN5
EN4
EN3
R/W
R/W
R/W
R/W
11
10
9
8
EN10
EN9
EN8
R/W
R/W
R/W
3
2
1
0
EN2
EN1
EN0
R/W
R/W
R/W
CHAPTER 3 INTERRUPT
2
OS. DMA
DERH
Initial value 00000000
B
DERL
Initial value 00000000
B
to
H
67
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