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CHAPTER 3 INTERRUPT
3.7.2
Each Register of EI
Extended intelligent I/O service (EI
types of 8-byte registers.
• Data counter (DCT: 2 bytes)
• I/O register address pointer (IOA: 2 bytes)
2
• EI
OS status register (ISCS: 1 byte)
• Buffer address pointer (BAP: 3 bytes)
The register reset values will become indeterminate.
■
Data counter (DCT)
Data counter (DCT) is 16-bit register. Specifies the number of bytes of transfer data. When a
data transfer is made, 1 is decremented. When the data counter (DCT) value becomes "0000
2
the EI
OS is completed.
bit
15 14
13
DCT
B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
: Readable/Writable
R/W
X
: Undefined
■
I/O register address pointer (IOA)
I/O register address pointer (IOA) is 16-bit register. Specifies the lower-order address (A15 to
A0) for the data transfer. The higher-order address (A23 to A16) is set to "00
000000
H
Figure 3.7-4 Configuration of I/O Register Address Pointer (IOA)
bit
15 14
13
IOA
A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W: Readable/Writable
X
:Undefined
82
2
2
OS) descriptor (ISD) is configurated by following 4
Figure 3.7-3 Configuration of Data Counter (DCT)
DCTH
12
11
10
9
8
7
to 00FFFF
can be used when specifying an address.
H
I/OAH
12
11
10
9
8
7
OS Descriptor (ISD)
DCTL
6
5
4
3
2
1
I/OAL
6
5
4
3
2
1
Initial value
0
XXXXXXXXXXXXXXXX
". The area from
H
Initial value
0
XXXXXXXXXXXXXXXX
",
H
B
B
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