Table of Contents
Advertisement
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.2 Configuration and Functions of DTP/External Interrupt Unit
Registers
This section describes the configuration and functions of the registers used in the
DTP/external interrupt unit.
■
List of registers for DTP/external interrupt unit
Figure 16.2-1 shows a list of the registers for the DTP/external interrupt unit.
bit
Address: 00000C
EN7
H
bit
Address: 00000D
ER7
H
bit
Address: 00000E
LB3
H
bit
Address: 00000F
LB7
H
■
Interrupt/DTP enable register (ENIR: Enable interrupt request register)
The bit configuration of the interrupt/DTP enable register (ENIR) is shown below.
ENIR
Address: 00000C
The interrupt/DTP enable register (ENIR) enables or disables an external interrupt/DTP request
for an external interrupt/DTP channel.
If the interrupt/DTP enable bits (ENs) of ENIR and the interrupt/DTP request flag bits (ENs) of
EIRR are all set to "1", an interrupt request for the corresponding interrupt/DTP pin is generated.
Signal inputs to this register are not interrupted during standby mode.
Note:
Please clear DTP/external interrupt factor bit (EIRR: ER) corresponding to immediately before
permitting DTP/external interrupt.
344
Figure 16.2-1 List of DTP/external interrupt unit registers
7
6
5
4
EN6
EN5 EN4 EN3
15
14
13
12
ER6
ER5 ER4 ER3
7
6
5
4
LA3
LB2
LA2
15
14
13
12
LA7
LB6
LA6
bit
7
6
5
EN7
EN6
EN5 EN4 EN3
H
R/W
R/W
R/W R/W R/W
3
2
1
0
EN2
EN1 EN0
11
10
9
8
ER2
ER1 ER0
3
2
1
0
LB1
LA1
LB0
LA0
11
10
9
8
LB5
LA5
LB4
LA4
4
3
2
1
EN2
EN1 EN0
R/W
R/W R/W
Interrupt/DTP enable register
(ENIR)
Interrupt/DTP source register
(EIRR)
Request level setting register
(ELVR)
Request level setting register
(ELVR)
0
Initial value
00000000
B
Advertisement
Table of Contents
