Fujitsu MB90480 Series Hardware Manual page 248

CHAPTER 12 16-BIT INPUT/OUTPUT TIMER
[bit12, bit11, bit10] MSI2, MSI1, MSI0
These bits specify the count with which a compare clear interrupt is masked. It consists of 3-
bit reload counter that reloads the count value every time the counter value reaches "000".
During writing to this register, the count value is also loaded, where mask count = specified
count (e.g., set to "010" when masked twice and the third time is interrupted). However, if
"000" is set, no interrupt cause is masked.
[bit9] ICLR
This bit is the interrupt request flag for compare clear. If the compare clear register and free-
running timer are found to have matching values by compare result, this bit is set to "1". If the
interrupt request permit bit (bit8: ICRE) is set, an interrupt occurs. This bit is cleared by
writing "0". Writing "1" has no effect. An instruction of the read-modify-write type always
reads "1".
0
1
[bit8] ICRE
This bit is the interrupt permit bit for compare clear. If this bit is set to "1" and the interrupt
flag (bit9: ICLR) is set to "1", then an interrupt occurs.
0
1
[bit7] IVF
This bit is the interrupt request flag of the free-running timer. If the free-running timer causes
an overflow or mode setting results in a match between the compare clear register and
compare results of free-running timer so that the counter is cleared, then the IVF bit is set to
"1". If the interrupt request permit bit (bit5: IVFE) is set, an interrupt occurs. This bit is cleared
by setting "0". Setting "1" has no effect. An instruction of the read-modify-write type reads
"1".
0
1
[bit6] IVFE
This bit is the interrupt permit bit for the free-running timer. If this bit is set to "1" when the
write flag (bit5: IVF) is set to "1", an interrupt occurs.
0
1
226
No interrupt request issued (initial value)
Interrupt request issued
Interrupt prohibited (initial value)
Interrupt permitted
No interrupt request used (initial value)
Interrupt request used
Interrupt prohibit (initial value)
Interrupt permit