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APPENDIX
Table D.5-2 Cycle Count Correction Values for Counting Execution Cycles
Internal register
Internal memory
Even address
Internal memory
Odd address
External data bus
16-bit even address
External data bus
16-bit odd address
External data bus
8-bits
*: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "D.8 F
List".
Note:
When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
Table D.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Internal memory
External data bus 16-bits
External data bus 8-bits
Note:
• When an external data bus is used, the cycle counts during which an instruction is made to wait
by ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
608
Operand
Cycle
count
+0
+0
+0
+1
+1
+1
Instruction
*
(b) byte
(c) word
Access
Cycle
count
count
1
+0
1
+0
1
+2
1
+1
1
+4
1
+4
Byte boundary
*
(d) long
Access
Cycle
count
count
1
+0
1
+0
2
+4
1
+2
2
+8
2
+8
2
MC-16LX Instruction
Word boundary
-
+2
-
+3
+3
-
*
Access
count
2
2
4
2
4
4
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