Configuration Of Pwc Timer - Fujitsu MB90480 Series Hardware Manual

25.2

Configuration of PWC Timer

The PWC timer consists of the PWC control/statue register, PWC data buffer, and
divide ratio control register.
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Block diagram of PWC timer
Figure 25.2-1 shows a block diagram of the PWC timer.
PWCR read
Reload
Data transfer
Overflow
Control circuit
Measurement
start edge
Measurement
end edge
Measurement end
interrupt request
Overflow interrupt request
15
Figure 25.2-1 Block diagram of the PWC timer
Error
ERR
detection
PWCR
16
16
16-bit up-count timer
Start edge
End edge
selection
selection
Divide ON/OFF
Edge
detection
PIS0/PIS1
ERR CKS0/CKS1
PWCSR
2
CHAPTER 25 PWC TIMER (ONLY MB90485 SERIES)
Clock
Timer
CKS1/CKS0
clear
Count enabled
8-bit
divider
Divide ratio selection
DIVR
Internal clock(machine clock/4)
2
2
Clock divider
3
2
Divider clear
Input
PWC0
waveform
PWC1
comparator
517