Timer Control Status Register (Tmcsr) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 11 16-BIT RELOAD TIMER (WITH THE EVENT COUNT FUNCTION)

11.2.1 Timer Control Status Register (TMCSR)

The timer control status register (TMCSR) controls 16-bit timer operation modes and
interrupts.
■ Timer Control Status Register (TMCSR)
High-order byte of the timer
control status register
Address:
ch.0 00005B
ch.1 00005F
Read/write
Initial value
Low-order byte of the timer
control status register
Address:
ch.0 00005A
ch.1 00005E
Read/write
Initial value
Note:
Rewrite a bit other than the UF, CNTE, and TRG bits when CNTE is "0".
[bit11 ,bit10] CSL1 and CSL0 (clock select 0, 1)
CSL1 and CSL0 bits are used to select a count clock. The following table lists the clock
sources to be selected:
Table 11.2-1 Function of CSL1 and CSL0 (Count Clock Select Bits)
CSL1
0
0
1
1
[bit9 to bit7] MOD2, MOD1, and MOD0
MOD2, MOD1, and MOD0 bits are used to set an operation mode and an I/O pin function.
The MOD2 bit is used to select an I/O function. If this bit is "0", the input pin (TIN) becomes
a trigger input pin. If a valid edge is input, the contents of the reload register are loaded to
the counter and the count operation continues. If this bit is "1", the gate counter mode is
entered. The input pin (TIN) becomes a gate input and the count operation continues only
while the active level is input.
184
Figure 11.2-2 Timer Control Status Register (TMCSR)
bit
15 14
H
H
(-) (-) (-)
(-) (-) (-)
bit 7 6
H
MOD0 OUTE OUTL RELD INTE
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0)
CSL0
0 φ/2
1 φ/2
0 φ/2
1 External event count mode
13 12 11 10
CSL1 CSL0 MOD2 MOD1
(-) (R/W) (R/W) (R/W) (R/W)
(-) (0) (0)
5 4 3
UF
(0) (0) (0)
Clock source (machine cycle φ = 16 MHz)
1
(0.125µs) [Initial value]
3
(0.5µs)
5
(2.0µs)
9 8
(0) (0)
2 1 0
CNTE TRG TMCSR
(0) (0)