Fujitsu MB90480 Series Hardware Manual page 19

Main changes in this edition
Page
All of the following descriptions are changed.
(μDMA → μDMAC)
-
(2M BIT FLASH MEMORY → 2M/3M BIT FLASH MEMORY)
(MB90F481/MB90F482 → MB90F481B/MB90F482B/MB90F488B/MB90F489B)
4 Table 1.1-2 MB90485 series product configuration is changed.
■ Package of corresponding products is added.
5
6 Figure 1.2-1 Block diagram of MB90480/485 Series is changed.
Figure 1.4-1 Pin assignment diagram of MB90480/485 series (QFP-100) is changed.
9
(Text in the figure is changed.)
Figure 1.4-2 Pin assignment diagram of MB90480/485 series (LQFP-100) is changed.
10
(Text in the figure is changed.)
❍ Crystal oscillation circuit is changed.
21 (Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. is
added.)
❍ Notes on using external clock is changed.
(Use of the external clock requires a connection with an external pin, as shown in Figure 1.7-1 "Use of exter-
nal clock". → To use external clock, drive only pin XO. Be sure to set up pin X1 to be open.)
❍ Note on operations during PLL clock mode is changed.
(If the PLL clock mode is selected, the microcontroller attempt to be working with the selfoscillating circuit
22
even when there is no external oscillator or external clock input is stopped.Performance of this operation,
however, cannot be guaranteed. → On this microcontroller, if in case the crystal oscillator breaks off or an
external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained
in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee
results of operations if such failure occurs.)
Table 3.2-2 Interrupt factors, interrupt vectors, and interrupt control registers is changed.
(*2: Please write "0" in the INTE bit, after prohibiting interrupt by setting the IL2 bit to IL0 bit of the inter-
48
rupt control register to "111
bit of TMCSR registers =1) to prohibit (INTE bit of TMCSR registers =0). is added.)
Figure 3.6-7 μDMAC processing procedure is changed.
75
78 to 88
3.7 Interrupt by Extended Intelligent I/O Service (EI
■ Reset factors ❍ Power-on reset of 4.1 Overview of Reset is changed.
96
(MB90F488B → MB90F488B/F489B)
Figure 5.3-2 Configuration of PLL output selection register (PLLOS) is changed.
(------X0
B
115
(PLL output selection bit → PLL output frequency doubling selection bit)
(Reserved bit → PLL input divided selection bit)
Table 5.3-2 Functions of bits for PLL output selection register (PLLOS) is changed.
116
(• The readout value is always 1. → • Read value is undefined.)
Changes (For details, refer to main body.)
", if the reload timer underflow interrupt setting is changed from enable (INTE
B
→ ------00
)
B
2
OS) is added.
xv