Table 2.3-1 Level indicated by interrupt level mask register (ILM)
ILM2
ILM1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
ILM0
Level value
0
0
1
1
0
2
1
3
0
4
1
5
0
6
1
7
CHAPTER 2 CPU
Permitted interrupt level
Interrupt prohibited
"0" only
Level value less than 1
Level value less than 2
Level value less than 3
Level value less than 4
Level value less than 5
Level value less than 6
35