Program Address Detect Control Status Register (Pacsr) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

21.3.2 Program Address detect Control Status Register (PACSR)

Program Address Detect Control Status Register
Address : 009E
Read/write
Initial value
This register provides control bits and status bit for the ROM correction function.
[bit 5~4]
These are the reserved bits, be sure to write ' 0'.
[bit 3]: AD1E (Compare Enable 1)
This is the ADR1 enable bit.
When this bit is at ' 1', this module compares the PADR1 register and the program counter. If there is
an agreement, the INT9 instruction is sent to the CPU.
[bit 2]:
This is a reserved bit.
[bit 1]: AD0E (Compare Enable 0)
This is the ADR0 enable bit.
When this bit is at ' 1', this module compares the PADR0 register and the program counter. If there is
an agreement, the INT9 instruction is sent to the CPU.
[bit 0]:
This is a reserved bit.
MB90580 Series
7 6
— —
H
(–) (–)
(–) (–)
5 4 3
— —
AD1E
(–) (–) (R/W)
(0) (0) (0)
Chapter 21: ROM Correction Module
21.3 Registers and Register Details
2 1 0
— —
AD0E PACSR
(–) (R/W) (–)
(0) (0) (0)
Bit number
293