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13.3.2 Counter control register (ch.1) upper (CCRH1)
This section describes the configuration and explains the function of counter control
register (ch.1) upper (CCRH1).
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Counter control register (ch.1) upper (CCRH1)
The bit configuration of the counter control register (ch.1) upper (CCRH1) is shown below.
Figure 13.3-3 Bit configuration of counter control register (ch.1) upper (CCRH1)
CCRH1
ch.1 Address: 000071
Counter control register (ch.1) upper (CCRH1) consists of bits that have the functions explained
below.
[bit14] CDCF (count direction reversal flag)
This bit is set when the count direction changes. It is set in the count start mode when the
count direction changes from up to down or from down to up.
The initialization (writing "0") is only permitted.
Read-modify-write type instructions read "1" irrespective of bit values.
CDCF
0
1
[bit13] CFIE (count direction reversal interrupt enable)
This bit is used to control interrupt output to the CPU if CDCF is defined. It generates an
interrupt in the count start mode when the count direction changes if this bit is set to "1".
CFIE
0
1
bit
15
14
13
-
CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 -0000000
H
R/W
R/W R/W R/W
No direction reversals (initial value)
One or more reversals of direction
Direction reversal interrupt output
Direction reversal interrupt output prohibit (initial value)
Direction reversal interrupt output permit
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER
12
11
10
9
R/W
R/W R/W
Direction reversal detection
8
Initial value
B
267
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