Interrupt Of 8/16-Bit Up/Down Counter/Timer - Fujitsu MB90480 Series Hardware Manual

13.4

Interrupt of 8/16-bit Up/Down Counter/Timer

The interrupt of the 8/16-bit up/down counter/timer occurs when the count direction is
changed only once during count start, when an match of comparison result is
detected, or when the overflow/underflow occurs.
The DMA transfer and extended intelligent I/O service (EI
the interrupt of the 8/16-bit up/down counter/timer.
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Interrupt of 8/16-bit up/down counter/timer
Table 13.4-1 shows the interrupt control bit and interrupt source of the 8/16-bit up/down counter/
timer.
Table 13.4-1 Interrupt of 8/16-bit Up/Down Counter/Timer
Interrupt request flag
Interrupt request output
enable bit
Interrupt generation source
CCRH0/OCR0 correspond to up/down counter pins (AIN0/BIN0/ZIN0).
CCRH1/OCR1 correspond to up/down counter pins (AIN1/BIN1/ZIN1).
● Count direction change interrupt
The operation for generating the count direction change interrupt is shown below.
• Bit14: CDCF flag of the counter control register (CCRH0/1) is set to "1".
• While bit13: CFIE of the interrupt request (CCRH 0/1) is enabled ("1"). When the count
direction is changed only once during count start, the interrupt occurs.
● Overflow/underflow interrupt
The operation for generating the overflow/underflow interrupt is shown below.
• Bit5: UDIE flag of the counter status register (CSR0/1) is set to "1".
• If bit3: OVFF or bit2: UDFF of the counter status register (CSR0/1) is set to "1", the interrupt
request occurs.
● Counter compare match interrupt
The operation for generating the compare interrupt is shown below.
• Bit6: CITE flag of the counter status register (CSR0/CSR1) is set to "1".
• When a comparison result between the UDCR value and RCR value using bit4: CMPF of the
counter status register (CSR0/1) matches, the interrupt request occurs.
Count direction
detection interrupt
CCRH0: CDCF (bit14) ch.0
CCRH1: CDCF (bit14) ch.1
CCRH0: CFIE (bit13) ch.0
CCRH1: CFIE (bit13) ch.1
Up/down counter
direction detection
CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER
2
OS) cannot be activated for
Overflow/
underflow interrupt
CSR0: OVFF (bit3) ch.0
UDFF (bit2)
CSR1: OVFF (bit3) ch.1
UDFF (bit2)
CSR0: UDIE (bit5) ch.0
CSR1: UDIE (bit5) ch.1
Overflow/underflow detec-
tion
Counter compare
match interrupt
CSR0: CMPF (bit4) ch.0
CSR1: CMPF (bit4) ch.1
CSR0: CITE (bit6) ch.0
CSR1: CITE (bit6) ch.1
Match between value of
up/down counter and that of
reload/compare register
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