Interrupt Of 16-Bit Reload Timer - Fujitsu MB90480 Series Hardware Manual

14.3

Interrupt of 16-Bit Reload Timer

The interrupt of the 16-bit reload timer occurs when underflow of the counter is
detected. The underflow interrupt of counter can activate the DMA transfer and
extended intelligent I/O service (EI
■
Interrupt of 16-bit reload timer
Table 14.3-1 shows the interrupt control bit and interrupt source of the 16-bit reload timer.
Table 14.3-1 Interrupt of 16-bit reload timer
Timer interrupt request flag
Interrupt request output enable bit
Interrupt generation source
When the value of the TMR value is decremented from "0000" to "FFFF" during the 16-bit timer
register (TMR) count operation, an underflow occurs. When an underflow occurs, the timer
interrupt request flag (UF = 1) in the timer control status register (TMCSR) is set. When an
underflow interrupt is enabled (INTE = 1), an interrupt request is generated.
■
Interrupt of 16-bit reload timer, DMA transfer, and EI
Table 14.3-2 shows the relationship between the interrupt source, interrupt vector, and interrupt
control register other than software interrupt.
Table 14.3-2 Interrupt source, interrupt vector, and interrupt control register
Interrupt source
16-bit free-running timer overflow,
16-bit reload timer underflow
❍: Interrupt request flag is cleared.
* : This interrupt source shares the interrupt source and interrupt number of other peripheral function. For
details, see Table 3.2-2.
Note:
If there are two interrupt sources in the same interrupt number, resource clears both interrupt request flags.
Therefore, when one of two sources uses the EI
The interrupt request enable bit of the relevant resource is set to 0 to execute the software polling
processing.
■
Correspondence to DMA transfer and EI
The 16-bit reload timer corresponds to the DMA transfer function and EI
To use DMA or EI
must be disabled.
2
OS).
Reload timer
μDMAC
2
EI OS
channel
clear
number
*
❍
12
2
OS/μDMAC function, other interrupt function cannot use.
2
OS function
2
OS function, other interrupt that shares the interrupt control register (ICR)
CHAPTER 14 16-BIT RELOAD TIMER
Underflow interrupt
TMCSR: UF (bit2)
TMCSR: INTE (bit3)
Underflow of 16-bit reload timer
2
OS
Interrupt vector Interrupt control register
Number Address Number
FFFF70
#35
H
Address
0000BC
ICR12
H
2
OS function.
303