Fujitsu MB90480 Series Hardware Manual page 470

CHAPTER 20 CHIP SELECTION FACILITY
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Block diagram of pin related to chip select facility
Figure 20.2-2 Block diagram of pin related to chip select facility
Port data register (PDR)
PDR Read
PDR Write
Port direction register
DDR Write
DDR Read
Standby control : Stop mode (SPL=1), timebase timer mode (SPL=1), watch mode (SPL=1)
448
Output latch
(DDR)
Direction latch
Peripheral function output
(CS0 to CS3)
Peripheral function output enable
Standby control
P-ch
Pin
N-ch
(SPL=1)