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CHAPTER 3 INTERRUPT
3.6.1
DMA Descriptor
The DMA descriptor is located in internal RAM within a range from "000100
"00017F
" consisting of 8 bytes x 16 channels.
H
■
DMA descriptor configuration
The DMA descriptor consists of 8 bytes x 16 channels. Each DMA descriptor has the
configuration shown in the Figure 3.6-2. Table 3.6-1 lists the relationship between channel
number and DMA descriptor address.
Descriptor
header address
70
Figure 3.6-2 Configuration of DMA descriptor
MSB
Upper 8 bits of data counter (DCTH)
Lower 8 bits of data counter (DCTL)
Upper 8 bits of I/O register address pointer (IOAH)
Lower 8 bits of I/O register address pointer (IOAL)
DMA control register (DMACS)
Upper 8 bits of buffer address pointer (BAPH)
Middle 8 bits of buffer address pointer (BAPM)
Lower 8 bits of buffer address pointer (BAPL)
" to
H
LSB
H
L
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