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Oscillation stabilization wait time
❍ Oscillation stabilization wait time of oscillation clock
The oscillator for source oscillation is stopped in the stop mode, and a oscillation stabilization
wait time must be provided. Specify the oscillation stabilization wait time selected with the
selection bits (WS1 and WS0) for the oscillation stabilization wait time of the clock selection
register (CKSCR).
Note:
Set "00
" in the selection bits (WS1 and WS0) for the oscillation stabilization wait time of the clock
B
selection register (CKSCR) only in the main clock mode.
❍ Oscillation stabilization wait time of PLL clock
In main clock mode, the PLL multiplication circuit stops. When changing to PLL clock mode, it is
necessary to reserve the PLL clock oscillation stabilization wait time. The CPU runs in main
clock mode till the PLL clock oscillation stabilization wait time has elapsed.
When the main clock mode is switched to PLL clock mode, the PLL clock oscillation stabilization
wait time is fixed at 2
In sub-clock mode, the main clock and PLL multiplication circuit stop. When changing to PLL
clock mode, it is necessary to reserve the main clock oscillation stabilization wait time and PLL
clock oscillation stabilization wait time. The oscillation stabilization wait times for main clock and
PLL clock are counted simultaneously according to the value specified in the oscillation
stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register. The
oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection
register must be selected accordingly to account for the longer of the main clock and PLL clock
oscillation stabilization wait times. The PLL clock oscillation stabilization wait time, however,
requires 2
WS1, WS0) in the clock selection register to "10
In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL
stop mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock
oscillation stabilization wait time. The oscillation stabilization wait times for the main clock and
PLL clock are counted simultaneously according to the value specified in the oscillation
stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register. The
oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection
register must be selected accordingly to account for the longer of main clock and PLL clock
oscillation stabilization wait time. The PLL clock oscillation stabilization wait time, however,
requires 2
WS1, WS0) in the clock selection register to "10
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Switching the clock mode
When the clock mode is switched, do not switch to low-power consumption mode and other
clock mode before this switching is completed. Confirm the completion of clock mode switching
by referring to the MCM and SCM bits of the clock selection register (CKSCR). If the mode is
switched to another clock mode or low-power consumption mode before completion of
switching, the mode may not be switched.
14
/HCLK (HCLK: oscillation clock).
14
/HCLK or more. Set the oscillation stabilization wait time selection bits (CKSCR:
14
/HCLK or more. Set the oscillation stabilization wait time selection bits (CKSCR:
CHAPTER 6 LOW-POWER CONSUMPTION MODE
" or "11
".
B
B
" or "11
".
B
B
149
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